The invention relates to a semiconductor device comprising a semiconductor body having a surface at least a non-volatile memory cell which comprises a non-volatile memory transistor, said memory transistor comprising a control electrode coupled capacitively to a charge storage region and source and drain zones of a first conductivity type which are separated from a layer-shaped portion of the semiconductor body adjoining said source and drain zones by a p-n junction, the layer-shaped portion being of a second conductivity type opposite to the first, a channel region of the memory transistor being present between the source and drain zones and being covered with an insulating layer which separates the charge storage region from the channel region, the charge storage region being separated from an injector by a thin insulating layer, charge transport being capable of occuring through said thin insulating layer by applying a suitable electric field to vary the quantity of charge stored in the charge storage region.
Such a memory transistor is known, for example, from IEEE transactions of Electron Devices, Vol ED-27, No 7, July, 1980, pp. 1211-1216. It relates to a p-channel memory transistor in which the charge storage region has the form of a floating conductive layer which is embedded in insulating material. The control electrode is separated from the floating conductive layer by an insulating layer present on the floating conductive layer. The injector has a p-type surface region spaced from the source and drain zones and provided in the layer-shaped portion of the semiconductor body, said p-type injector region and the layer-shaped portion comprising an electrical connection. The p-type injector region laterally adjoins a surface part of the layer-shaped region, which surface part is separated from the floating conductive layer by a thin insulating layer. Charge transport from and to the floating conductive layer may take place through said thin insulating layer. The layer-shaped portion of the semiconductor body may be set up at a reference potential, for example, ground. If the reference voltage is also applied to the control electrode and the injector region is set up at such a high negative voltage that the p-n junction between the injector region and the layer-shaped portion is operated in the avalanche breakdown mode, hot charge carriers are generated in the semiconductor body and hot electrons can reach the floating conductive layer through the thin insulating layer. As a result of this the floating conductive layer is charged negatively. If the injector region is then set up at the reference potential and a suitably large negative voltage is applied to the control electrode, electrons can flow from the floating conductive layer to the semiconductor body through the thin insulating layer by tunneling. As a result of this the floating conductive layer is charged less negatively and can also be charged positively.
The known memory transistor described is one example of the various types of memory transistors which are used in programmable memories usually referred to as EEPROM's or E.sup.2 PROM's or EAROM's or EPROM's. Such non-volatile memory transistors can generally be erased electrically or by means of U.V.-radiation and then be written (programmed) again electrically.
The charge storage region may be non-conductive intermediate layer embedded in an insulating dielectric layer, for example, as in so-called MNOS-memory transistors. In MNOS-memory transistors the charge representing the information is stored in the proximity of the boundary layer between two different dielectric layers, for example, silicon oxide and silicon nitride. The change of the information content is said memory transistors is usually produced by means of the tunneling of charge carriers between the charge storage region and the underlying channel region of the transistor which serves as the injector.
In other memory transistors the charge storage region hence has the shape of a floating conductive layer. In this case, instead of injection of hot carriers generated by means of avalanche breakdown for charging and discharging or injecting hot carriers in one direction and tunneling charge carriers to the semiconductor body in the other direction, the tunneling of charge carriers in both directions may also be used for writing and erasing. In memory transistors in which the charge transport in both directions is based on a tunneling mechanism, the injector is often formed by a part of the drain zone of the transistor, which part is separated from the floating conductive layer by a very thin insulating layer having a thickness of, for example, a few tens of Angstroms.
The control electrode is usually provided on an insulating layer above the floating conductive layer. However, the control electrode may be also present entirely or partly is the semiconductor body. Although the injector is usually present in the semiconductor body in the form of a doped zone, the injector may also be present in the form of a conductive layer above the floating conductive layer. Furthermore, the last-mentioned conductive layer may also be used in combination with an injector present in the semiconductor body, one injector serving of the supply of charge carriers to the charge storage region and the other injector serving for the drain of charge carriers from the charge storage region.
All the memory transistors indicated hereinbefore have in common that information in the form of charge is stored in the charge storage region, in which on the one hand it must be possible to vary the charge state sufficiently rapidly with voltage and currents which are as low as possible and on the other hand to preserve the charge sufficiently long once it has been stored. For this retaining of stored charge it is notably necessary that in the charged condition of the charge storage region no undesired transport of charge carriers takes place which can discharge the charge storage region. In this charged condition charge is present in the capacities of which the charge storage region forms a part, for example, the coupling capacity between the charge storage region and the control electrode and the coupling capacity between the charge storage region and the injector. A voltage which may result in the leaking away of stored charge is then present across said capacity. Moreover, applying voltages to the connections of the memory transistor may also stimulate undesired charge transport from or to the charge storage region.
It will be apparent that as the writing and erasing of the memory transistors can more easily be carried out, that is to say, the writing and erasing take place with smaller currents and preferably at lower voltages, the realization of the desired long retaining time can easily lead to a comparatively low yield of manufacture of the semiconductor device in question.
The leaking away of charge can furthermore be stimulated by particular circumstances, for example, an operating temperature which, whether or not temporarily, is higher than was anticipated. The reliable operation of the semiconductor device can be endangered by these and other causes.